It is a conventional dilemma that, while a drastic improvement of an operating frequency is needed in response to an increasingly superfine LSI process, a wire delay time caused by a wire resistance is increased. It is therefore very difficult to simultaneously optimize properties of an LSI at a designing stage, the characteristics being such as an operating frequency and power consumption. Because reduction of power consumption is a most significant challenge especially for recent high-performance LSIs, some of the recent high-performance LSIs are configured at a designing stage to be less power-consuming, and a timing adjustment for optimizing a clock frequency is performed after an wafer process is completed.
Related art on a clock skew adjustment is described in the following publications, for example:    (1) U.S. Pat. No. 6,192,092 (date of patent: Feb. 20, 2001);    (2) Nasser A. Kurd, Javed S. Barkatullah, Rommel O. Dizon, Thomas D. Fletcher, and Paul D. Madland, “A Multigigahertz Clocking Scheme for the Pentium(R) 4 Microprocessor”, IEEE Journal of Solid State Circuits, Vol. 36, No. 11, November 2001, pp. 1647-1653; and    (3) Daniel Deleganes, Jonathan Douglas, Badari Kommandur, Marek Patyra, “Designing a 3 GHz, 130 nm, Pentium(R) 4 Processor”, 2002 Symposium on VLSI Circuits Digest of Technical Papers. 
FIGS. 18 and 19 illustrate art related to the clock skew adjustment, the art being excerpted from the United States Patent and the theses mentioned above.
FIG. 18 schematically illustrates clock skew detection and a compensating circuit in the related art. In FIG. 18, clock skew values of two clock domains, i.e. a local clock domain 1 and a local clock domain 2, are detected at a skew detection, and then transferred to a tester interface. A global clock duty cycle control adjusts a ratio of a duty cycle of a clock supplied to an LSI as a whole.
A tester (not shown) sets an adjustment value for a skew adjustment control circuit comp1 control or comp2 control so as to minimize a skew value. In accordance with the value set by the tester, a circuit of FIG. 19 described later adjusts a timing of each clock by adjusting rising time or falling time of the local clock domain 1 or the local clock domain 2. Values supplied from the tester are respectively programmed in a fixing manner into a prom by a prom comp1 setting and a prom comp2 setting, so that the values are stored.
FIG. 19 more specifically illustrates the clock skew compensating circuit of FIG. 18.
In FIG. 19, a first stage of a programmable delay buffer 200 is provided for adjusting the falling time, and a second stage of the programmable delay buffer 200 is provided for adjusting the rising time. Each of the first stage and the second stage includes a PMOS pull-up transistor, eight inverters 215 or 225, and eight switches (pull-down paths s0 to s7). A 5-bit control register 130 and a 3-to-8 decoder 140 decode a control signal (control bits), and supply the control signal to the programmable delay buffer 200. The 5-bit control register 130 and the 3-to-8 decoder 140 are the comp1 control and the comp2 control, respectively.
In this arrangement, the falling time and the rising time are adjusted by using the number of switches (among the eight switches) that are turned ON by the adjustment value supplied from the tester.
However, because this adjustment method requires a large number of switches and inverters, there is a problem that a large circuit size is required in order to perform a clock skew adjustment.
In connection with this problem, there is a problem of trade-off between a freedom of adjustment (an adjustment range and adjustment fineness) and a small circuit size. For example, in order to double the freedom of adjustment (the adjustment range or the adjustment fineness) in the circuit of FIG. 19, it is necessary to increase the number of the switches from eight to 16. As a result, the circuit size of an adjusted part is also doubled. On the other hand, if the number of the switches is decreased, the circuit size is decreased, but a sufficient adjustment cannot be attained because the adjustment range and the adjustment fineness are insufficient.